The present invention relates to apparatus for testing integrated circuits and more particularly to arrangements for testing and burning-in integrated circuits at the wafer level.
The desirability of testing integrated circuits at the wafer level is of particular interest since determination of failures at this early stage can significantly reduce costs. At present, the testing of integrated circuit chips in wafer form is generally limited in scope, or a slow procedure only permitting extensive testing of a few chips at a time. That is, wafer level testing is often performed using a mechanical stepping device with each circuit tested sequentially. Further, wafer level testing as presently available often does not lend itself to accelerated failure procedures, such as burn in, and thus requires still further testing at a later stage in the manufacturing process.
An example of an integrated circuit test arrangement is shown in U.S. Pat. No. 5,148,103, issued Sep. 15, 1992, which utilizes a flexible membrane supporting a probe arrangement for testing one chip at a time. This patent employs a terminating resistor or chip on the membrane for providing high impedance, low capacitance loading. Simultaneous testing of a few circuit chips at one time is described in U.S. Pat. No. 5,012,187, issued Apr. 30, 1991. This patent describes a test head comprising a flexible membrane of circuit board material carrying probe bumps for contacting the pads of the product chips. Transmission lines connect the probe bumps to the edge of the membrane for coupling each of the circuit chips to a test apparatus.
As can be appreciated, testing of more than one chip at a time generally will require isolation of defective chips that draw excessive current. This difficulty can be resolved by employing a separate switch or fuse circuit for each product chip undergoing test, as for example, is described in the IBM Technical Disclosure Bulletins, Vol. 32, No. 6B, November 1989 and Vol. 33, No. 8, January 1991. In the latter publications, power and test lines are carried in the kerf regions of the product wafer to connect the circuit chips to a remote tester.
In a different approach, IBM Technical Disclosure Bulletin, Vol. 34 No. 8, dated January 1992 describes a test head, solderable by means of pad bumps to the front surface of a product wafer for sequentially, or simultaneously, testing the circuit chips of the product wafer. The test head includes a multiplicity of active chips each having a switch circuit for disconnecting faulty chips of the product wafer.
These prior test arrangements fail to accommodate the currents resulting from simultaneous testing of a multiplicity of chips as for example, testing at one time, substantially all of the chips provided within a conventionally sized integrated circuit wafer.
On the other hand, PCT Application WO 93/04375 International Application Number PCT/US92/07044, International Filing Date: Aug. 23, 1991 describes an arrangement for simultaneous burn-in testing of a wafer in which a test substrate carries both power and ground planes connected through vias to deformable solder bumps on the surface of the substrate. For burn-in testing, the substrate is urged against the face of a product wafer with its solder bumps engaging the pads of the wafer chips.
Isolation resistors provided on the substrate connect its power and ground planes to the integrated circuit chips to accommodate shorted chips. This use of isolation resistors, while permitting burn-in testing, limits other testing modes and also fails to adequately resolve the problem of short circuited product chips, which draw large currents and reduce the voltage available for application to neighboring chips.
It is therefore an object of the present invention is to provide an improved structure for testing and burning-in integrated circuit chips at the wafer level.
It is still another object of the present invention to provide an improved test arrangement for simultaneously testing and burning-in a plurality of the product chips on an integrated circuit wafer simultaneously.
It is yet another object of the present invention to provide an improved power distribution structure that provides an externally specified Vdd voltage to each product chip on an integrated circuit wafer, the voltage substantially independent of the current drawn by each chip and its neighbors, and substantially independent of the presence of shorted chips on the product wafer.
It is yet another object of the present invention to provide an improved power distribution structure that effectively removes shorted product chips from power distribution.
It is a feature of the present invention that a substrate having a low thermal coefficient of expansion (TCE), such as glass ceramic, aluminum nitride, Kovar, Invar, silicon, or a laminated metal, such as Kovar, copper-Invar-copper, tungsten, or molybdenum is used to test product wafers.
It is a feature of the present invention that a voltage regulator circuit is provided for each product chip to be tested.
It is a feature of one embodiment of the present invention that power is distributed through a glass ceramic substrate to test chips having voltage regulators and then to the product wafer.
It is a feature of another embodiment of the present invention that power supply current is distributed through the back surface of test chips having voltage regulators and then to the product wafer.
It is another feature of the present invention that a voltage regulator provided for each circuit chip to be tested has a voltage that can be externally controlled.
It is another object of the present invention to disconnect signal I/O from a chip having a short.
It is yet a further object of the present invention to provide an improved test head having a plurality of active test chips including voltage regulator circuits.
It is yet a further object of the present invention to provide a portable apparatus having the product wafer aligned to the test head, the apparatus ready for insertion into a tester or burn-in chamber.
It is a feature of the present invention that a vacuum clamp having a seal on the back of the product wafer or on the back of the test head provides a portable aligned apparatus ready for insertion into a tester or burn-in chamber.
It is a feature of the present invention to provide a means of maintaining temperature control of the product wafer while allowing it to conform to the probe array, which may be non-planar.
These and other objects, features, and advantages of the invention are accomplished by an apparatus for simultaneously contacting a plurality of integrated circuit product chips having signal I/O, ground, and power pads, the product chips on a product wafer having a front surface and a back surface, the apparatus connectable to a power supply, the apparatus comprising: a test head connectable to a plurality of the product chips on the product wafer, said test head comprising at least one test chip electrically connectable to the product chips, said at least one test chip having a front and a back surface; and a plurality of voltage regulators on said at least one test chip, said regulators connectable between the power supply and the power pads on the product chips.
Another aspect of the invention is accomplished by an apparatus capable of simultaneously contacting substantially all of the integrated circuit product chips on a product wafer having a front surface and a back surface, the product chips having signal I/O, ground, and power pads, the apparatus connectable to a power supply, the apparatus comprising: a test head having a first side and a second side; and said first side of said test head capable of simultaneously contacting power pads on substantially all of the product chips on the product wafer, said test head having means for distributing power from the power supply to said contacting means, said test head comprising a ceramic material, a metal, or a laminated metal having a thermal coefficient of expansion matching that of the product wafer.
Another aspect of the invention is accomplished by a method for testing or burning-in substantially all of the integrated circuit product chips on a product wafer, the product chips having signal I/O, ground, and power pads, the method comprising the steps of: a) contacting pads of substantially all of the product chips on the product wafer simultaneously with a test head comprising a ceramic material, a metal, or laminated metal having a thermal coefficient of expansion matching that of the product wafer; b) providing power from a power supply to power pads of the product chips through said test head; and c) testing or burning-in the plurality of product chips on the wafer through said test head.
Another aspect of the invention is accomplished by an apparatus capable of connecting a plurality of the chips on a product wafer to a test system to
simultaneously test or burn-in the product chips, the product wafer having a front and a back surface, the apparatus comprising: a test head having a front and a back surface and a plurality of contacts; means for electrically connecting said plurality of contacts to the test system; and
means for connecting said contacts to the product wafer wherein said connecting means comprises probes and a vacuum clamp provided between the product wafer and said test head, a vacuum seal for said vacuum clamp provided to the back surface of at least one of the product wafer and said test head.
Another aspect of the invention is accomplished by an apparatus capable of wafer level test and burn-in, the apparatus comprising: means for contacting pads on substantially all the product chips on the product wafer at room temperature and at a selected burn-in temperature; and means for providing power to all the product chips to be tested or burned-in on the product wafer at a voltage level independent of the presence of shorted chips on the product wafer.
Another aspect of the invention is accomplished by an apparatus for controlling the temperature of a product wafer having a back surface, comprising: an array of pistons capable of contacting most of the area of the back surface of the wafer; and a means for providing force to each piston of said array capable of providing thermal contact between said piston and the wafer to control the temperature of the wafer.
A test head of the apparatus can includes a carrier, such as a ceramic substrate that may be formed of a material such as glass ceramic, and test chips, including voltage regulator circuits, that are attached to the substrate. The regulators control the magnitude of the voltage and make the voltage delivered to each product chip under test conditions insensitive to the presence of shorted chips on the wafer and insensitive to the magnitude of the current drawn by each chip. The regulators are variable to allow selection of a precise voltage. They are also gated, or capable of being tri-stated (brought to a high impedance state), to enable selective on or off switching of the regulator circuit Thus, the associated product chip can be removed from contact with power. Alternatively, a compliance current can be set for the regulators to limit current to shorted chips. Decoupling capacitance is provided at the output of the regulators, enabling higher speed testing. The glass ceramic substrate, having many thick copper layers, is capable of providing the unregulated voltage to the test chips and to distribute regulated voltage from the test chips to product chips on the product wafer with minimal voltage drops.